r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 794

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 19 Controller Area Network (RCAN-ET)
Rev. 1.00 Sep. 21, 2007 Page 768 of 1124
REJ09B0402-0100
Notes:
1.
2.
3.
IRR[0] = 1, GSR[3] = 1 (automatically)
(automatically in hardware reset only)
SW reset could be performed at any time by setting MCR[0] = 1.
Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.
If there is no TXPR set, RCAN-ET will receive the next incoming message.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
RTR, IDE, MBC, MBIMR, DART,
(STD-ID, EXT-ID, LAFM, DLC,
ATX, NMC, Message-Data)*
Clear Required IMR Bits
Power On/SW Reset*
Set Bit Timing (BCR)
Configure MCR[15]
Mailbox Setting
clear IRR[0] Bit
Clear MCR[0]
MCR[0] = 1
1
Figure 19.8 Reset Sequence
2
Reset Sequence
Configuration Mode
Receive*
Detect 11 recessive bits and
RCAN-ET is in Tx_Rx Mode
Set TXPR to start transmission
or stay idle to receive
Join the CAN bus activity
3
GSR[3] = 0?
Yes
Transmission_Reception
(Tx_Rx) Mode
Transmit*
3
No