r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 319

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

10.3.9
TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and
TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in
channel 3 but the MTU2 has no TSYCR.
Bit
7
6
5
4
Bit Name
CE0A
CE0B
CE0C
CE0D
Timer Synchronous Clear Register (TSYCR)
Initial value:
Initial
Value
0
0
0
0
R/W:
Bit:
CE0A
R/W
7
0
R/W
R/W
R/W
R/W
R/W
CE0B
R/W
6
0
Description
Clear Enable 0A
Enables or disables counter clearing when the TGFA
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_0
1: Enables counter clearing by the TGFA flag in TSR_0
Clear Enable 0B
Enables or disables counter clearing when the TGFB
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_0
1: Enables counter clearing by the TGFB flag in TSR_0
Clear Enable 0C
Enables or disables counter clearing when the TGFC
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFC flag in TSR_0
1: Enables counter clearing by the TGFC flag in TSR_0
Clear Enable 0D
Enables or disables counter clearing when the TGFD
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFD flag in TSR_0
1: Enables counter clearing by the TGFD flag in TSR_0
CE0C
R/W
5
0
CE0D
R/W
4
0
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
CE1A
R/W
3
0
Rev. 1.00 Sep. 21, 2007 Page 293 of 1124
CE1B
R/W
2
0
CE2A
R/W
1
0
CE2B
R/W
0
0
REJ09B0402-0100