r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 614

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 14 Serial Communication Interface (SCI)
14.4.6
Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
14.17 shows an example of SCI operation for multiprocessor format reception.
Rev. 1.00 Sep. 21, 2007 Page 588 of 1124
REJ09B0402-0100
MPIE
RDRF
SCRDR
value
RXD
MPIE
RDRF
SCRDR
value
RXD
Multiprocessor Serial Data Reception
1
1
Start
bit
Start
bit
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
0
0
Figure 14.17 Example of SCI Operation in Reception
MPIE = 0
MPIE = 0
D0
D0
ID1
D1
D1
Data (ID1)
Data (ID2)
RXI interrupt
request
(multiprocessor
interrupt)
generated
RXI interrupt
request
(multiprocessor
interrupt)
generated
D7
D7
(a) Data does not match station’s ID
(b) Data matches station’s ID
MPB
MPB
1
1
SCRDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
SCRDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Stop
bit
Stop
bit
1
1
Start
bit
Start
bit
0
0
D0
D0
If not this station’s ID,
MPIE bit is set to 1
again
Matches this station’s ID,
so reception continues,
and data is received in RXI
interrupt processing routine
D1
D1
Data (Data1)
Data (Data2)
ID2
ID1
D7
D7
MPB
MPB
0
0
RXI interrupt request is
not generated,
and SCRDR retains
its state
Stop
bit
Stop
bit
1
1
MPIE bit is set to 1
again
Idle state
(mark state)
Idle state
(mark state)
Data2
1
1