r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 769

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(2)
The General Status Register (GSR) is a 16-bit read-only register that indicates the status of
RCAN-ET.
• GSR (Address = H'002)
Initial value:
Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 5 — Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error
Passive or not. This bit will be set high as soon as the RCAN-ET enters the Error Passive state and
is cleared when the module enters again the Error Active state (this means the GSR5 will stay high
during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5
and GSR0 must be considered.
Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep
state or not. Please note that the clearing time of this flag is not the same as the setting time of
IRR12.
Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP.
RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits
sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 5 : GSR5
0
1
Bit 4 : GSR4
0
1
R/W:
General Status Register (GSR)
Bit:
15
R
0
-
14
R
0
-
13
Description
RCAN-ET is not in Error Passive or in Bus Off status (Initial value)
[Reset condition] RCAN-ET is in Error Active state
RCAN-ET is in Error Passive (if GSR0=0) or Bus Off (if GSR0=1)
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or if Error Passive Test
Mode is selected
Description
RCAN-ET is not in the Halt state or Sleep state (Initial value)
Halt mode (if MCR1=1) or Sleep mode (if MCR5=1)
[Setting condition] If MCR1 is set and the CAN bus is either in intermission or
idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving
to Bus Off when MCR14 and MCR6 are both set
R
0
-
12
R
0
-
11
R
0
-
10
R
0
-
R
9
0
-
R
8
0
-
Section 19 Controller Area Network (RCAN-ET)
R
7
0
-
Rev. 1.00 Sep. 21, 2007 Page 743 of 1124
R
6
0
-
GSR5
R
5
0
GSR4
R
4
0
GSR3
R
3
1
REJ09B0402-0100
GSR2
R
2
1
GSR1
R
1
0
GSR0
R
0
0