r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 153
r5f71374an80fpv
Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F71374AN80FPV.pdf
(1154 pages)
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[Legend]
x:
Bit
7, 6
5, 4
3, 2
1, 0
Don't care.
Bit Name
CDA[1:0]
IDA[1:0]
RWA[1:0]
SZA[1:0]
Initial
Value
00
00
00
00
R/W
R/W
R/W
R/W
R/W
Description
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Instruction Fetch/Data Access Select A
Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
Read/Write Select A
Select the read cycle or write cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
Operand Size Select A
Select the operand size of the bus cycle for the channel
A break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Note:
data access cycle
When specifying the operand size, specify the
size which matches the address boundary.
Rev. 1.00 Sep. 21, 2007 Page 127 of 1124
Section 7 User Break Controller (UBC)
REJ09B0402-0100
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