r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 642

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 15 Synchronous Serial Communication Unit (SSU)
15.4
15.4.1
A transfer clock can be selected from seven internal clocks and an external clock. Before using
this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an
internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the
clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin.
When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.
15.4.2
The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 15.2
shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting
is valid.
Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data
is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the
LSB.
Rev. 1.00 Sep. 21, 2007 Page 616 of 1124
REJ09B0402-0100
(1) When CPHS = 0
(2) When CPHS = 1
(CPOS = 0)
(CPOS = 1)
(CPOS = 0)
(CPOS = 1)
SSI, SSO
SSI, SSO
Operation
Transfer Clock
Relationship of Clock Phase, Polarity, and Data
SSCK
SSCK
SSCK
SSCK
SCS
SCS
Figure 15.2 Relationship of Clock Phase, Polarity, and Data
Bit 0
Bit 0
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5
Bit 6
Bit 6
Bit 7
Bit 7