r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 663

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
[3]
Note: Hatching boxes represent SSU internal operations.
[1]
[2]
No
Figure 15.17 Flowchart Example of Simultaneous Transmission/Reception
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Clear TE and RE in SSER to 0
Write transmit data to SSTDR
Read receive data in SSRDR
RDRF automatically cleared
TDRE automatically cleared
End transmission/reception
Clear TEND in SSSR to 0
transmission/reception?
One bit time quantum
Read TDRE in SSSR.
Read TEND in SSSR
Consecutive data
Initial setting
Read SSSR
ORER = 1?
TDRE = 1?
RDRF = 1?
Yes
TEND = 1?
elapsed?
Start
Yes
Yes
Yes
No
(Clock Synchronous Communication Mode)
No
Yes
No
No
No
Yes
Error processing
[4]
[5]
Section 15 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
[2] Check the SSU state and write transmit data:
[3] Check the SSU state:
[4] Receive error processing:
[5] Procedure for consecutive data transmission/reception:
Specify the transmit/receive data format.
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE bit
is automatically cleared to 0 and transmission is started
by writing data to SSTDR.
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Rev. 1.00 Sep. 21, 2007 Page 637 of 1124
REJ09B0402-0100