r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 709

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

16.8
16.8.1
The I
is for I
For details, refer to section 24, Power-Down Modes.
16.8.2
A stop condition or repeated start condition should be issued after the fall of the ninth clock pulse
is recognized. The fall of the ninth clock pulse can be recognized by checking the SCLO bit in the
I
specific timing under the conditions 1 or 2 shown below, the condition may not be output
successfully. Issuance under other than these conditions will succeed with no problem.
1. When the SCL signal did not rise within the time specified in section 16.7, Bit Synchronous
2. When the bit synchronous circuit is activated because the low-level periods of the eighth and
16.8.3
Do not issue a start condition and stop condition in sequence. If a start condition and stop
condition are to be issued in sequence, be sure to transmit a slave address before issuing the stop
condition.
2
C bus control register 2 (ICCR2). When a stop condition or repeated start condition is issued at a
Circuit, due to the load of the SCL bus (load capacitance or pull-up resistor).
ninth clock pulses are extended by the slave device.
2
C2 operation can be disabled or enabled using the standby control register. The initial setting
2
C2 operation to be halted. Access to registers is enabled by clearing module standby mode.
Usage Note
Module Standby Mode Setting
Issuance of Stop Condition and Repeated Start Condition
Issuance of a Start Condition and Stop Condition in Sequence
Rev. 1.00 Sep. 21, 2007 Page 683 of 1124
Section 16 I
2
C Bus Interface 2 (I
REJ09B0402-0100
2
C2)