r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 242

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 9 Bus State Controller (BSC)
9.4.4
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC. It also specifies
the application of priority in transfer operations and enables or disables the functions that have the
effect of decreasing numbers of cycles over which the DTC is active. The differences in DTC
operation made by the combinations of the DTLOCK, CSSTP1, and DTBST bits settings are
described in section 8.5.9, DTC Bus Release Timing.
Setting the CSSTP2 bit can improve the transfer performance of the DTC transfer when the
DTLOCK bit is 0. Furthermore, setting the CSSTP3 bit selects whether or not access to the
external space by the CPU takes priority over DTC transfer.
The DTC short address mode is implemented by setting the DTSA bit. For details of the short
address mode, see section 8.4, Location of Transfer Information and DTC Vector Table.
A DTC activation priority order can be set up for the DTC activation sources. The DTPR bit
selects whether or not this priority order is valid or invalid when multiple sources issue activation
requests before DTC activation. Do not modify this register while the DTC is active.
Initial value:
Rev. 1.00 Sep. 21, 2007 Page 216 of 1124
REJ09B0402-0100
Bit
5 to 2
1, 0
R/W:
Bit:
DTLOCK CSSTP1
R/W
Bus Function Extending Register (BSCEHR)
15
0
Bit Name

HW[1:0]
R/W
14
0
13
R
0
-
Initial
Value
All 0
00
CSSTP2
R/W
12
0
DTBST DTSA
R/W
11
0
R/W
R
R/W
R/W
10
0
CSSTP3
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Delay Cycles from RD and WRL Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRL
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R/W
9
0
DTPR
R/W
8
0
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R
2
0
-
R
1
0
-
R
0
0
-