r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 705

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

16.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.4 shows the
contents of each interrupt request.
Table 16.4 Interrupt Requests
When the interrupt condition described in table 16.4 is 1, the CPU executes an interrupt exception
handling. Interrupt sources should be cleared in the exception handling. The TDRE and TEND
bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is
automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time
when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an
excessive data of one byte may be transmitted. The TDRE, TEND, and RDRF bits are
automatically cleared while the specified number of transfers by the DTC is in progress; however,
the TDRE, TEND, and RDRF bits are not cleared automatically when the transfer is complete.
Interrupt Request
Transmit data Empty IITXI
Transmit end
Receive data full
STOP recognition
NACK receive
Arbitration lost/
overrun error
I
2
C2 Interrupt Sources
Abbreviation Interrupt Condition
IITEI
IIRXI
IISTPI
IINAKI
(TDRE=1)
(TEND=1)
(RDRF=1)
(STOP=1)
{(NACKF=1)+(AL=1)}
(NAKIE=1)
•
•
•
•
(STIE=1)
(TIE=1)
(TEIE=1)
(RIE=1)
•
Rev. 1.00 Sep. 21, 2007 Page 679 of 1124
I
√
√
√
√
√
√
2
C Mode
Section 16 I
Clock
Synchronous
Mode
√
√
√
×
×
√
2
C Bus Interface 2 (I
REJ09B0402-0100
DTC
Activation
√
×
√
×
×
×
2
C2)