r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 686

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 16 I
16.4
The I
by setting FS in SAR.
16.4.1
Figure 16.3 shows the I
following a start condition always consists of eight bits.
[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
Rev. 1.00 Sep. 21, 2007 Page 660 of 1124
REJ09B0402-0100
(a) I
(b) I
S
1
S
1
2
2
2
C bus interface 2 can communicate either in I
C bus format (FS = 0)
C bus format (Start condition retransmission, FS = 0)
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receive device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
SDA
SCL
Operation
I
SLA
SLA
2
2
C Bus Format
7
7
C Bus Interface 2 (I
S
1
1
R/W
R/W
1
1
SLA
1-7
2
C bus formats. Figure 16.4 shows the I
A
A
1
1
R/W
8
2
C2)
DATA
DATA
n1
n
Figure 16.3 I
Figure 16.4 I
9
A
m1
A
1
A/A
m
1
1-7
DATA
2
S
1
C Bus Formats
2
C Bus Timing
2
8
C bus mode or clock synchronous serial mode
SLA
A/A
1
7
A
9
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
P
1
1
2
R/W
C bus timing. The first frame
1
1-7
DATA
A
1
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
8
DATA
n2
9
A
m2
P
A/A
1
1
P

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