r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 623

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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14.7.6
When the external clock source is used for the clock for synchronization, input the external clock
after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified
through the DTC. If a transmit clock is input within four cycles after SCTDR is modified, a
malfunction may occur (figure 14.22).
When data is written to SCTDR by activating the DTC by a TXI interrupt, the TEND flag value
becomes undefined. In this case, do not use the TEND flag as the transmit end flag.
14.7.7
TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock
after the SCK external clock is changed from 0 to 1.
TE and RE must be set to 1 only while the SCK external clock is 1.
14.7.8
SCI operation can be disabled or enabled using the standby control register. The initial setting is
for SCI operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 24, Power-Down Modes.
TDRE
SCK
TXD
Note: When using the external clock, t must be set to larger than 4 cycles.
Note on Using DTC
Note on Using External Clock in Clock Synchronous Mode
Module Standby Mode Setting
Figure 14.22 Example of Clock Synchronous Transfer Using DTC
t
D0
D1
D2
D3
Section 14 Serial Communication Interface (SCI)
D4
Rev. 1.00 Sep. 21, 2007 Page 597 of 1124
D5
D6
REJ09B0402-0100
D7

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