r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 777

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bits 11 to 10: Reserved
Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has
been received but the existing message in the matching Mailbox has not been read as the
corresponding RXPR or RFPR is already set to ‘1’ and not yet cleared by the CPU. The received
message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message
Control) bit. This bit is cleared when
(by writing ‘1’) or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set
cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position
has no effect.
Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for
transmission has been successfully sent (corresponding TXACK flag is set) or has been
successfully aborted (corresponding ABACK flag is set). The related TXPR is also cleared and
this mailbox is now ready to accept a new message data for the next transmission. In effect, this
bit is set by an OR’ed signal of the TXACK and ABACK bits not masked by the corresponding
MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits
are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR.
Writing to this bit position has no effect.
Bit 9: IRR9
0
1
Bit 8: IRR8
0
1
Description
No pending notification of message overrun/overwrite
[Clearing condition] Clearing of all bit in UMSR/setting MBIMR for all UMSR
set (initial value)
A receive message has been discarded due to overrun condition or a
message has been overwritten
[Setting condition] Message is received while the corresponding RXPR
and/or RFPR =1 and MBIMR =0
Description
Messages set for transmission or transmission cancellation request NOT
progressed. (Initial value)
[Clearing Condition] All the TXACK and ABACK bits are cleared/setting
MBIMR for all TXACK and ABACK set
Message has been transmitted or aborted, and new message can be stored
[Setting condition]
When one of the TXPR bits is cleared by completion of transmission or
completion of transmission abort, i.e., when a TXACK or ABACK bit is set (if
MBIMR=0).
all bit in UMSR
(Unread Message Status Register)
Section 19 Controller Area Network (RCAN-ET)
Rev. 1.00 Sep. 21, 2007 Page 751 of 1124
REJ09B0402-0100
. It is also
are cleared