r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 431

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

10.4.9
A/D converter start requests can be issued in channel 4 by making settings in the timer A/D
converter start request control register (TADCR), timer A/D converter start request cycle set
registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4).
The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or
TADCORB_4, and when their values match, the function issues a respective A/D converter start
request (TRG4AN or TRG4BN).
A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
TADCR.
1. Example of Procedure for Specifying A/D Converter Start Request Delaying Function
Figure 10.79 shows an example of procedure for specifying the A/D converter start request
delaying function.
Set A/D converter start request cycle
• Set the timing of transfer
• Set linkage with interrupt skipping
• Enable A/D converter start
from cycle set buffer register
request delaying function
A/D Converter Start Request Delaying Function
A/D converter start request
A/D converter start request
Figure 10.79 Example of Procedure for Specifying A/D Converter
delaying function
delaying function
Start Request Delaying Function
[1]
[2]
[1] Set the cycle in the timer A/D converter start request cycle
[2] Use bits BF1 and BF2 in the timer A/D converter start
Notes: 1. Perform TADCR setting while TCNT_4 is stopped.
• Specify whether to link with interrupt skipping through bits
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable
buffer register (TADCOBRA_4 or TADCOBRB_4) and timer
A/D converter start request cycle register (TADCORA_4 or
TADCORB_4). (The same initial value must be specified in
the cycle buffer register and cycle register.)
request control register (TADCR) to specify the timing of
transfer from the timer A/D converter start request cycle
buffer register to A/D converter start request cycle register.
ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
A/D conversion start requests (TRG4AN or TRG4BN).
2. Do not set BF1 to 1 when complementary PWM mode
3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE,
is not selected.
DT4AE, or DT4BE to 1 when complementary PWM
mode is not selected.
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 1.00 Sep. 21, 2007 Page 405 of 1124
REJ09B0402-0100