r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 258

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 9 Bus State Controller (BSC)
The states that do not allow bus arbitration are shown below.
1. Between the read and write cycles of a TAS instruction
2. Multiple bus cycles generated when the data bus width is smaller than the access size (for
To prevent device malfunction while the bus mastership is transferred to the external device, the
LSI negates all of the bus control signals before bus release. When the bus mastership is received,
all of the bus control signals are first negated and then driven appropriately. In addition, to prevent
noise while the bus control signal is in the high impedance state, pull-up resistors must be
connected to these control signals.
Bus mastership is transferred to the external device at the boundary of bus cycles. Namely, bus
mastership is released immediately after receiving a bus request when a bus cycle is not being
performed. The release of bus mastership is delayed until the bus cycle is complete when a bus
cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being
performed, a bus cycle may be performing internally, started by inserting wait cycles between
access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has
been released by looking at the CSn signal or other bus control signals.
The external bus release by the BREQ and BACK signal handshaking requires some overhead. If
the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition.
Reducing the cycles required for master to slave bus mastership transitions streamlines the system
design.
The LSI has the bus mastership until a bus request is received from the external device. Upon
acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases
the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI
acknowledges the negation (high level) of the BREQ signal that indicates the slave has released
the bus, it negates the BACK signal and resumes the bus usage.
Processing by this LSI continues even while bus mastership is released to an external device,
unless an external device is accessed. When an external device is accessed, the LSI enters the state
of waiting for bus mastership to be returned.
While the bus is released, sleep mode, software standby mode, and deep software standby mode
cannot be entered.
The bus release sequence is as follows. The address bus and data bus are placed in a high-
impedance state synchronized with the rising edge of CK. The bus mastership acknowledge signal
is asserted 0.5 cycles after the above high impedance state, synchronized with the falling edge of
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example, between bus cycles when longword access is made to a memory with a data bus
width of 8 bits)