r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 264

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 9 Bus State Controller (BSC)
Figure 9.14 shows an example of the timing of read access when the external bus width is greater
than or equal to the data width and Iφ:Bφ = 4:1. Transfer from the L bus to the external bus is
performed in the same way as for write access. In the case of reading, however, values output onto
the external bus must be transferred to the CPU. Transfers from the external bus to the I bus and
from the I bus to the L bus are again performed in synchronization with rising edges of the
respective bus clocks. In the actual operation, transfer from the external bus to the L bus takes one
φ period. In the case shown in the figure, where n = 2 and m = 0, access takes 3 × Iφ + 3 × Bφ + 1
× Iφ.
Iφ
L bus
Bφ (CK)
I bus
External bus
For access by the DTC, the access cycles are obtained by subtracting the cycles of Iφ required for
L-bus access from the access cycles required for access by the CPU.
Rev. 1.00 Sep. 21, 2007 Page 238 of 1124
REJ09B0402-0100
Iφ
L bus
Bφ (CK)
I bus
External bus
(1 + n) × Iφ
Figure 9.13 Timing of Write Access to Word Data in External Memory
(1 + n) × Iφ
Figure 9.14 Timing of Read Access with Condition Iφ:Bφ = 4:1 and
When Iφ:Bφ = 2:1 and External Bus Width is 8 Bits
prolonged by a period of m.
(3 + m) × Bφ
This access period is
External Bus Width ≥ Data Width
First external access
(3 + m) × Bφ
prolonged by a period of m.
prolonged by a period of o.
Second external access
This access period is
This access period is
External access
(2 + o) × Bφ
In this example, m = 0 and o = 0.
For the numbers of cycles by which
m and o prolong the access process,
see section 9.4, Register Descriptions.
In this example, m = 0.
For the numbers of cycles by which
m prolongs the access process,
see section 9.4, Register Descriptions.
1 × Iφ