r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 696

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 16 I
16.4.6
This module can be operated with the clock synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1)
Figure 16.13 shows the clock synchronous serial transfer format.
The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
Rev. 1.00 Sep. 21, 2007 Page 670 of 1124
REJ09B0402-0100
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICDRR
ICDRS
Data Transfer Format
RDRF
SCL
SDA
SDA
SCL
User
Clock Synchronous Serial Format
2
C Bus Interface 2 (I
Figure 16.13 Clock Synchronous Serial Transfer Format
Figure 16.12 Slave Receive Mode Operation Timing (2)
SCL
SDA
A
9
Bit 7
1
2
C2)
Bit 0
Bit 6
Data 1
2
Bit 1 Bit 2 Bit 3 Bit 4
Bit 5
3
Bit 4
4
Bit 3
5
[3] Set ACKBT
Bit 2
6
Bit 5 Bit 6
Bit 1
7
[3] Read ICDRR [4] Read ICDRR
Bit 0
Bit 7
8
A
9
Data 1
Data 2

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