r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 790

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 19 Controller Area Network (RCAN-ET)
(7)
The MBIMR1 and MBIMR0 are 16-bit read / write registers. The MBIMR only prevents the
setting of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt,
IRR[2] – Remote Frame Request Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] –
Message OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the
corresponding bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and
IRR[9]) but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR.
Similarly when a mailbox has been configured for transmission, a mask prevents the generation of
an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent the RCAN-ET from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the
ABACK bit for abortion of the transmission.
A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be
masked. At reset all mailbox interrupts are masked.
• MBIMR0
Initial value:
Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0
respectively.
Rev. 1.00 Sep. 21, 2007 Page 764 of 1124
REJ09B0402-0100
Bit[15:0]: RFPR0
0
1
Bit[15:0]: MBIMR0 Description
0
1
R/W:
Mailbox Interrupt Mask Register (MBIMR)
Bit:
R/W
15
1
R/W
14
1
R/W
13
Description
[Clearing Condition] Writing ‘1’ (Initial value)
Corresponding Mailbox received Remote Frame
[Setting Condition] Completion of remote frame receive in corresponding
mailbox
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
MBIMR0[15:0]
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1