r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 680

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 16 I
16.3.5
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
Rev. 1.00 Sep. 21, 2007 Page 654 of 1124
REJ09B0402-0100
Bit
7
6
I
2
Bit Name
TDRE
TEND
2
C Bus Status Register (ICSR)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
0
R/W:
Bit:
2
C2)
TDRE
R/W
7
0
R/W
R/W
R/W
TEND
R/W
6
0
Description
Transmit Data Register Empty
[Setting conditions]
[Clearing conditions]
Transmit End
[Setting conditions]
[Clearing conditions]
RDRF NACKF STOP AL/OVE
R/W
5
0
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
When 0 is written to TDRE after reading TDRE = 1
When data is written to ICDRT
DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clock synchronous serial format
When 0 is written to TEND after reading TEND = 1
When data is written to ICDRT
DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
R/W
4
0
R/W
3
0
R/W
2
0
R/W
AAS
1
0
R/W
ADZ
0
0
2
C bus

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