r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 955

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 22.12.
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased. Especially the part where the SCO
bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. Specify 1/4 (initial
value) as the frequency division ratios of an internal clock (If), a bus clock (Bf), and a
peripheral clock (Pf) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 22.9.2, Areas for Storage of the Procedural
Program and Data for Programming.
set download destination
JSR FTDAR setting+32
Select on-chip program
Start erasing procedure
to be downloaded and
Set the FPEFEQ and
After clearing VBR,
FUBRA parameters
execute download
Set FKEY to H'A5
set SCO to 1 and
Clear FKEY to 0
FPFR=0 ?
Initialization
DPFR = 0?
by FTDAR
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
(3.1)
Figure 22.12 Erasing Procedure
No
Rev. 1.00 Sep. 21, 2007 Page 929 of 1124
JSR FTDAR setting+16
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
Required block
End erasing
FPFR=0 ?
completed?
erasing is
Erasing
1
Yes
Yes
Section 22 Flash Memory
Clear FKEY and erasing
No
error processing
REJ09B0402-0100
(3.2)
(3.3)
(3.4)
(3.5)
(3.6)