r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 154

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 7 User Break Controller (UBC)
7.3.4
BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select
one of two data buses for break condition A.
Initial value:
Initial value:
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Rev. 1.00 Sep. 21, 2007 Page 128 of 1124
REJ09B0402-0100
Bit
31 to 0 BDA31 to
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9
Bit Name
BDA0
R/W
R/W
Break Data Register A (BDRA)
31
15
0
0
bits 15 to 8 and 7 to 0 in BDRA as the break data.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Break Data Bit A
Stores data which specifies a break condition in channel
A.
If the I bus is selected in BBRA, the break data on IDB is
set in BDA31 to BDA0.
If the L bus is selected in BBRA, the break data on LDB
is set in BDA31 to BDA0.
R/W
R/W
25
0
9
0
BDA8
R/W
R/W
24
0
8
0
BDA7
R/W
R/W
23
0
7
0
BDA6
R/W
R/W
22
0
6
0
BDA5
R/W
R/W
21
0
5
0
BDA4
R/W
R/W
20
0
4
0
BDA3
R/W
R/W
19
0
3
0
BDA2
R/W
R/W
18
0
2
0
BDA1
R/W
R/W
17
0
1
0
BDA0
R/W
R/W
16
0
0
0