r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 524

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 12 Port Output Enable (POE)
12.3.1
ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE2 pin input modes,
controls the enable/disable of interrupts, and indicates status.
Initial value:
Rev. 1.00 Sep. 21, 2007 Page 498 of 1124
REJ09B0402-0100
Bit
15
14
Notes:
R/W:
Bit:
1.
2.
Bit Name
POE2F
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
Input Level Control/Status Register 1 (ICSR1)
15
R
0
-
R/(W)*
POE2F POE1F POE0F
14
0
1
R/(W)*
13
0
Initial
value
0
0
1
R/(W)*
12
0
1
R/W
R
R/(W)*
11
R
0
-
10
R
0
-
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
POE2 Flag
This flag indicates that a high impedance request has
been input to the POE2 pin.
[Clearing conditions]
[Setting condition]
R
9
0
-
By writing 0 to POE2F after reading POE2F = 1
(when the falling edge is selected by bits 5 and 4 in
ICSR1)
By writing 0 to POE2F after reading POE2F = 1 after
a high level input to POE2 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 5 and 4 in ICSR1)
When the input set by ICSR1 bits 5 and 4 occurs at
the POE2 pin
R/W
PIE1
8
0
R
7
0
-
R
6
0
-
R/W*
POE2M[1:0]
5
0
2
R/W*
4
0
2
R/W*
POE1M[1:0]
3
0
2
R/W*
2
0
2
R/W*
POE0M[1:0]
1
0
2
R/W*
0
0
2

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