r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 637

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
1
0
Bit Name
RDRF
CE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
•
[Clearing conditions]
•
•
•
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. Data reception does not
continue while the CE bit is set to 1. Serial transmission
also does not continue. Reset the SSU internal
sequencer by setting the SRES bit in SSCRL to 1
before resuming transfer after incomplete error.
[Setting conditions]
•
•
[Clearing condition]
•
Section 15 Synchronous Serial Communication Unit (SSU)
When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
When writing 0 after reading RDRF = 1
When reading receive data from SSRDR
When the DTC is activated by an SSRXI interrupt
and receive data is read into SSRDR while the
DISEL bit in MRB of the DTC is 0
When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
When writing 0 after reading CE = 1
Rev. 1.00 Sep. 21, 2007 Page 611 of 1124
REJ09B0402-0100