r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 183

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
8.1
• Transfer possible over any number of channels:
• Chain transfer
• Three transfer modes
• The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
• Short address mode specifiable
• Bus release timing selectable from five types
• Priority of the DTC activation selectable from two types
Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*.
Note: When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR
DTCHX10A_000020030600
Multiple rounds of data transfer is executed in response to a single activation source
Chain transfer is only possible after data transfer has been done for the specified number of
times (i.e. when the transfer counter is 0)
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
address space directly
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
must be set to 1.
Features
Section 8 Data Transfer Controller (DTC)
Rev. 1.00 Sep. 21, 2007 Page 157 of 1124
Section 8 Data Transfer Controller (DTC)
REJ09B0402-0100

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