r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 470

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.11 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.129 shows the timing in this case.
10.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection
With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs
during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2
write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this
point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued.
Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0,
TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare
match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input
capture operation. The timing is shown in figure 10.130.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
Rev. 1.00 Sep. 21, 2007 Page 444 of 1124
REJ09B0402-0100
Figure 10.129 Contention between Buffer Register Write and Input Capture
MPφ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer register
Buffer register write cycle
M
Buffer register
T1
address
N
T2
M
N