r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 447

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3
and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in
channel 0 are not set by the occurrence of an input capture.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one
each for channels 1 and 2.
10.5.2
DTC Activation
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt in
each channel or the overflow interrupt in channel 4. For details, see section 8, Data Transfer
Controller (DTC).
A total of 20 MTU2 input capture/compare match interrupts and overflow interrupts can be used
as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, five for
channel 4, and three for channel 5.
Rev. 1.00 Sep. 21, 2007 Page 421 of 1124
REJ09B0402-0100