r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 262

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 9 Bus State Controller (BSC)
a single Bφ clock cycle when Iφ: Bφ = 4:2, transfer of data from the L bus to the I bus takes (3 +
n) × Iφ (n = 0 to 1) (3 × Iφ is indicated in figure 9.52). The relation between the timing of data
output to the L bus and the rising edge of Bφ depends on the state of program execution. In the
case shown in the figure, where n = 0 and m = 0, the time required for access is 3 × Iφ + 1 × Bφ +
2 × Pφ.
Figure 9.12 shows an example of timing of read access to the peripheral bus when Iφ:Bφ:Pφ =
4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for writing. In
the case of reading, however, values output onto the peripheral bus need to be transferred to the
CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the L bus are
performed in synchronization with the rising edge of the respective bus clocks, a period of 2 × Iφ
is actually required because Iφ ≥ Bφ ≥ Pφ. In the case shown in the figure, where n = 0 and m = 1,
the time required for access is 3 × Iφ + 2 × Bφ + 2 × Pφ + 2 × Iφ.
Rev. 1.00 Sep. 21, 2007 Page 236 of 1124
REJ09B0402-0100
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
Figure 9.11 Timing of Write Access to On-Chip Peripheral I/O Registers
Figure 9.12 Timing of Read Access to On-Chip Peripheral I/O Registers
(3 + n) × Iφ
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
(1 + m) × Bφ
(3 + n) × Iφ
When Iφ:Bφ:Pφ = 4:2:2
When Iφ:Bφ:Pφ = 4:2:1
(1 + m) × Bφ
2 × Pφ
2 × Pφ
2 × Iφ