r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 731

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r5f71374an80fpv

Manufacturer Part Number
r5f71374an80fpv
Description
32-bit Risc Microcomputer Superh?? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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TRGAN
(MTU2, MTU2S trigger signal)
Notes: 1. Sample-and-hold circuit for GrA and GrB
17.4.4
A/D conversion is activated by the A/D conversion start triggers (TRGAN, TRG0N, TRG4N, and
TRG4BN) from the MTU2 and A/D conversion start triggers (TRGAN, TRG4AN, and TRG4BN)
from the MTU2S. To enable this function, set the TRGE bit in ADCR to 1 and clear the EXTRG
bit to 0. After this setting is made, if an A/D conversion start trigger from the MTU2 or MTU2S is
generated, the ADST bit is set to 1. The timing between the setting of the ADST bit and the start
of the A/D conversion is the same for all A/D conversion activation soures.
The A/D conversion start trigger must be input after ADCR, ADSTRGR, and ADANSR registers
have been set.
converter
ADDR
ADST
ADF
A/D
2. Sample-and-hold circuit common to all channels
A/D Converter Activation by MTU2 and MTU2S
Figure 17.5 A/D Conversion Timing (Single-Cycle Scan Mode)
Waiting
t
D
hold time (t
Sampling and
and-hold*
Sample-
SPLSH
1
)
A/D conversion time (t
OFC
t
OFC
hold time (t
Sampling and
and-hold*
Rev. 1.00 Sep. 21, 2007 Page 705 of 1124
CONV
Sample-
Pφ = 32 MHz: 1.56 µs
Pφ = 40MHz: 1.25 µs
Conversion time
)
per channel
SPL
50 states
2
)
A/D conversion
Section 17 A/D Converter (ADC)
REJ09B0402-0100
Waiting
End of A/D
conversion

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