r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 791

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

(8)
This register is a 16-bit read/conditionally write register and it records the mailboxes whose
contents have not been accessed by the CPU prior to a new message being received. If the CPU
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox
is received, the corresponding UMSR bit is set to ‘1’. This bit may be cleared by writing a ‘1’ to
the corresponding bit location in the UMSR. Writing a ‘0’ has no effect.
If a mailbox is configured as transmit box, the corresponding UMSR will not be set.
• UMSR0
Initial value:
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition
has occurred for Mailboxes 15 to 0.
Bit[15:0]: UMSR0
0
1
R/W:
Unread Message Status Register (UMSR)
Bit:
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
0
14
0
13
Description
[Clearing Condition] Writing ‘1’ (initial value)
Unread received message is overwritten by a new message or overrun
condition
[Setting Condition] When a new message is received before RXPR or RFPR
is cleared
0
12
0
11
0
10
0
9
0
UMSR0[15:0]
8
0
Section 19 Controller Area Network (RCAN-ET)
7
0
Rev. 1.00 Sep. 21, 2007 Page 765 of 1124
6
0
5
0
4
0
3
0
REJ09B0402-0100
2
0
1
0
0
0