r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 606

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 14 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 14.11 shows an example of SCI transmit operation.
Rev. 1.00 Sep. 21, 2007 Page 580 of 1124
REJ09B0402-0100
Synchronization
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register
(SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is
started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and
then the TXD pin holds the states.
If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.
Serial data
TDRE
TEND
clock
Transfer direction
TXI interrupt
request
Figure 14.11 Example of SCI Transmit Operation
Bit 0
Data written to SCTDR
and TDRE flag cleared
to 0 by TXI interrupt handler
LSB
Bit 1
One frame
TXI interrupt
request
Bit 7
MSB
Bit 0
Bit 1
Bit 6
TEI interrupt
request
Bit 7