r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 717

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Bit
4
3, 2
1
Bit Name
ADIE

TRGE
Initial
Value
0
All 0
0
R/W
R/W
R
R/W
Trigger Enable
Description
A/D Interrupt Enable
Enables or disables the generation of A/D conversion end
interrupts (ADI_3 and ADI_4) to the CPU. Operating
modes must be changed when the ADST bit is 0 to
prevent incorrect operations.
When A/D conversion ends and the ADF bit in ADSR is
set to 1 and this bit is set to 1, ADI_3 or ADI_4 is sent to
the CPU. By clearing the ADF bit or the ADIE bit to 0,
ADI_3 and ADI_4 can be cleared.
0: Generation of A/D conversion end interrupt is disabled
1: Generation of A/D conversion end interrupt is enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Enables or disables A/D conversion start by the external
trigger input (ADTRG) or A/D conversion start triggers
from the MTU2 and MTU2S (TRGAN, TRG0N, TRG4AN,
and TRG4BN from the MTU2 and TRGAN, TRG4AN, and
TRG4BN from the MTU2S). For selection of the external
trigger and A/D conversion start trigger from the MTU2 or
MTU2S, see the description of the EXTRG bit.
0: A/D conversion start by the external trigger or an A/D
1: A/D conversion start by the external trigger or an A/D
conversion start trigger from the MTU or MTU2S is
disabled
conversion start trigger from the MTU2 or MTU2S is
enabled
Rev. 1.00 Sep. 21, 2007 Page 691 of 1124
Section 17 A/D Converter (ADC)
REJ09B0402-0100