r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 674

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.3.2
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I
Rev. 1.00 Sep. 21, 2007 Page 648 of 1124
REJ09B0402-0100
Bit
7
6
I
2
Bit Name
BBSY
SCP
2
C Bus Control Register 2 (ICCR2)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
1
R/W:
Bit:
2
C2)
BBSY
R/W
7
0
R/W
R/W
R/W
R/W
SCP
6
1
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start/stop conditions
in master mode. With the clock synchronous serial
format, this bit is always read as 0. With the I
format, this bit is set to 1 when the SDA level changes
from high to low under the condition of SCL = high,
assuming that the start condition has been issued. This
bit is cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high, assuming
that the stop condition has been issued. Write 1 to
BBSY and 0 to SCP to issue a start condition. Follow
this procedure also when transmitting a repeated start
condition. Write 0 in BBSY and 0 in SCP to issue a stop
condition.
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A repeated start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. Even if 1 is written to
this bit, the data will not be stored.
SDAO SDAOP SCLO
R/W
5
1
R/W
4
1
R
3
1
R
2
1
-
IICRST
R/W
1
0
2
C bus interface 2.
R
0
1
-
2
C bus is
2
C bus