r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 567

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

14.3.6
SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt
requests and selects the transmit/receive clock source. The CPU can always read and write to
SCSCR.
Bit
7
6
Serial Control Register (SCSCR)
Bit Name
TIE
RIE
Initial value:
Initial
value
0
0
R/W:
Bit:
R/W
TIE
7
0
R/W
R/W
R/W
R/W
RIE
6
0
Description
Transmit Interrupt Enable
Enables or disables a transmit-data-empty interrupt
(TXI) to be issued when the TDRE flag in the serial
status register (SCSSR) is set to 1 after serial transmit
data is sent from the transmit data register (SCTDR) to
the transmit shift register (SCTSR).
TXI can be canceled by clearing the TDRE flag to 0
after reading TDRE = 1 or by clearing the TIE bit to 0.
0: Transmit-data-empty interrupt request (TXI) is
1: Transmit-data-empty interrupt request (TXI) is
Receive Interrupt Enable
Enables or disables a receive-data-full interrupt (RXI)
and a receive error interrupt (ERI) to be issued when
the RDRF flag in SCSSR is set to 1 after the serial data
received is transferred from the receive shift register
(SCRSR) to the receive data register (SCRDR).
RXI can be canceled by clearing the RDRF flag after
reading RDRF =1. ERI can be canceled by clearing the
FER, PER, or ORER flag to 0 after reading 1 from the
flag. Both RXI and ERI can also be canceled by
clearing the RIE bit to 0.
0: Receive-data-full interrupt (RXI) and receive-error
1: Receive-data-full interrupt (RXI) and receive-error
R/W
TE
5
0
disabled
enabled
interrupt (ERI) requests are disabled
interrupt (ERI) requests are enabled
R/W
RE
4
0
Section 14 Serial Communication Interface (SCI)
MPIE
R/W
3
0
Rev. 1.00 Sep. 21, 2007 Page 541 of 1124
R/W
TEIE
2
0
R/W
1
0
CKE[1:0]
R/W
0
0
REJ09B0402-0100