r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 218

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Section 8 Data Transfer Controller (DTC)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in
transfer information plus 1).
+ Σ (J
•
•
•
•
•
•
Number of execution cycles = I
S
S
+ K
S
+ L
S
+ M
S
) + N
S
I
J
K
L
M
N
8.5.9
DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus mastership after a vector read, NOP cycle generation after a vector read,
transfer information read, a single data transfer, or transfer information writeback. The DTC does
not release the bus mastership during transfer information read, single data transfer, or transfer
information writeback.
The bus mastership release timing can be specified through the bus function extending register
(BSCEHR). For details see section 9.4.4, Bus Function Extending Register (BSCEHR). The
difference in bus mastership release timing according to the register setting is summarized in table
8.11. Settings other than settings 1 to 5 are not allowed. The setting must not be changed while the
DTC is active.
Figure 8.16 is a timing chart showing an example of bus mastership release timing.
Rev. 1.00 Sep. 21, 2007 Page 192 of 1124
REJ09B0402-0100