HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1074

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
(2)
Data transmission in smart card mode includes error signal sampling and retransmit processing.
An example of transmit processing is shown in figure 30.5.
Step (1) to step (6) of figure 30.5 correspond to the following operation.
1. Follow the initialization procedure above to initialize the smart card interface.
2. Confirm that the ERS bit (error flag) in SCSSR is cleared to 0.
3. Repeat steps (2) and (3) until it can be confirmed that the TDRE flag in SCSSR is set to 1.
4. Write transmit data to SCTDR, and perform transmission. At this time, the TDRE flag is
5. When performing continuous data transmission, return to step (2).
6. When transmission is ended, clear the TE bit to 0.
Interrupt processing can be performed in the above series of processing.
When the TIE bit is set to 1 to enable interrupt requests and if transmission is started and the
TDRE flag is set to 1, a transmit data empty interrupt (TXI) request is issued. When the RIE bit is
set to 1 to enable interrupt requests and if an error occurs during transmission and the ERS flag is
set to 1, a transmit/receive error interrupt (ERI) request is issued.
For details, refer to Interrupt Operations in section 30.4.5, Data Transmit/Receive Operation.
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automatically cleared to 0. When transmission of the start bit is started, the TEND flag is
automatically cleared to 0, and the TDRE flag is automatically set to 1.
Serial Data Transmission
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010