HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 729

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
20.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 20.11 and 20.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in
2. When the slave address matches in the first frame following detection of the start condition,
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICCKS1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
ICDRR
ICDRT
ICDRS
TDRE
TEND
SCL
SDA
SDA
SCL
User
TRS
Slave Receive Operation
Figure 20.10 Slave Transmit Mode Operation Timing (2)
A
9
Bit 7
1
Bit 6
2
Bit 5
3
Data n
Bit 4
[3] Clear TEND
4
Bit 3
5
Bit 2
6
[4] Read ICDRR (dummy read)
Bit 1
Slave transmit mode
after clearing TRS
7
Bit 0
8
Section 20 I
9
A
2
C Bus Interface (IIC)
[5] Clear TDRE
Page 669 of 1414
Slave receive
mode