HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 660

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Serial Communication Interface with FIFO (SCIF)
Page 600 of 1414
Bit
4
3, 2
1
0
Bit Name Initial Value R/W Description
RE
—
CKE1
CKE0
0
All 0
0
0
R/W Receive Enable
R
R/W
R/W
Enables or disables the SCIF serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Reserved
These bits are always read as 0. The write value should
always be 0.
Clock Enable 1and 0
These bits select the SCIF clock source. The bits CKE1
and CKE0 should be set before selecting the SCIF
operating mode by SCSMR.
00: Internal clock, SCK pin used for input pin (input signal
01: Internal clock, SCK pin used for synchronous clock
10: External clock, SCK pin used for clock input*
11: External clock, SCK pin used for clock input*
Notes: 1. When the data sampling is executed using on-
is ignored)*
output*
2. The serial mode register (SCSMR) and FIFO
2. In synchronous mode, a clock with a
3. In asynchronous mode, input the clock which
2
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
control register (SCFCR) should be set to
select the receive format and reset the receive
FIFO before setting the RE bit to 1.
chip baud rate generator, CKE1 and CKE0
should be set to 00.
frequency equal to the bit rate is output. When
the channel 0 is used as the IrDA interface,
CKE1 and CKE0 should be set to 01.
is appropriate for the sampling rate. For
example, when the sampling rate is 1/16,
input the clock frequency 8 times the bit rate.
When the external clock is not input, CKE1
and CKE0 should be set to 00.
When the SCK pin is set as an I/O port pin,
CKE1 and CKE0 should be set to 00.
1
2
1
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
3
3