HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 733

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Set RCVD in ICCR1 to 1
Clear STOP in ICSR.
Dummy-read ICDRR
Clear TEND in ICSR
Clear TDRE in ICSR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
Mater receive mode
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Figure 20.15 Sample Flowchart for Master Receive Mode
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Note: 1. Do not activate an interrupt during the execution of steps [1] to [3].
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Clear TEND, select master receive mode, and then clear TDRE.*
Set acknowledge to the transmit device.*
Dummy-read ICDDR.*
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data last.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of receive data.
Wait for the last byte to be receive.
2. When one byte is received, steps [2] to [6] are skipped; step [7] is executed
after step [1]. Setp [8] is ICDRR dummy read.
1
Section 20 I
2
C Bus Interface (IIC)
Page 673 of 1414
1
*
2