HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1295

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(3)
This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit
board. When this instruction is executed, output pins are used to output test data (previously set by
the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board,
and input pins are used to latch test results into the boundary scan register from the printed circuit
board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is
scanned-in when test data (N-1) is scanned out.
Data loaded into the output pin boundary scan register in the Capture-DR state is not used for
external circuit testing (it is replaced by a shift operation).
The upper four bits of the instruction code are B'0000.
(4)
A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the IDCODE mode
stipulated by JTAG. When the H-UDI is initialized (TRST is asserted or TAP is in the Test-Logic-
Reset state), the IDCODE mode is entered.
(5)
A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the CLAMP or
HIGHZ mode stipulated by JTAG.
36.5.2
1. Boundary scan mode does not cover the following signals:
2. When the EXTEST, CLAMP, and HIGHZ commands are set, fix the RESETP pin low.
3. Fix the CA pin high, during boundary scan.
4. When a boundary scan test for other than BYPASS and IDCODE is carried out, fix the
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
⎯ Clock-related signals (EXTAL, XTAL, EXTAL_USB, XTAL_USB, EXTAL_RTC,
⎯ System- and E10A-related signals (RESETP, RESETM, CA, ASEMD0)
⎯ H-UDI-related signals (TCK, TDI, TDO, TMS, TRST)
⎯ IIC-related signals (IIC_SCL/PTE6, IIC_SDA/PTE5)
⎯ Analog-related signals (AN0/PTF1, AN1/PTF2, AN2/PTF3, AN3/PTF4, DA0/PTF5,
ASEMD0 pin high.
EXTEST
IDCODE
CLAMP, HIGHZ
XTAL_RTC, CKIO)
DA1/PTF6, USB1_P, USB1_M, USB2_P, USB2_M)
Points for Attention
Section 36 User Debugging Interface (H-UDI)
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