HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 527

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
11.5
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are
controlled by software through FRQCR. The methods are described below.
11.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC1
4. The processor pauses internally and the WDT starts incrementing. The internal and peripheral
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
11.5.2
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC1 and IFC0 = 00 and PFC2 to PFC0 = 011.
2. Set the IFC1, IFC0, and PFC2 to PFC0 bits to the new division ratio. The values that can be set
3. The clock is immediately supplied at the new division ratio.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
WDT. The following must be set:
TME bit in WTCSR = 0: WDT stops
CKS2 to CKS0 bits in WTCSR: Division ratio of WDT count clock
WTCNT: Initial counter value
and IFC0 bits and PFC2 to PFC0 bits.
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin.
operating again. The WDT stops after it overflows.
are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the
wrong value is set, the processor will malfunction.
Changing Frequency
Changing Multiplication Rate
Changing Division Ratio
Section 11 Clock Pulse Generator (CPG)
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