HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 251

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
• Software (Initial Page Write Handler) Operations
4.5.5
If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the
SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the
SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific
instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to
H
address error and to H'0D0 for a TLB protection violation exception. In addition, a vector offset
for TLB miss exception is H'100. For details, refer to section 7.4.3, Exception in Repeat Control
Period.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
′
070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU
The software must execute the following operations:
A. Retrieve the required page table entry from external memory.
B. Set the D bit of the page table entry in the external memory to 1.
C. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table
D. If using software for way selection for entry replacement, write the desired value to the RC
E. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
F. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
entry in the external memory to the PTEL register.
field in MMUCR.
RTE instruction must be issued after two LDTLB instructions.
MMU Exception in Repeat Loop
Section 4 Memory Management Unit (MMU)
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