HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 885

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
25.3.28 Data Status Register (DASTS)
DASTS indicates whether the IN FIFO data register contains valid data. DASTS is set to 1 when
data written to IN FIFO is enabled by writing PKTE in TRG to 1, and cleared when all data has
been transmitted to the host. In case of a dual-configuration FIFO for endpoint 2, this bit is cleared
to 0 when both sides are empty.
25.3.29 FIFO Clear Register 0 (FCLR0)
FCLR is a one shot register to clear the FIFO buffers for endpoints 0 to 3. Writing 1 to a bit clears
the data in the corresponding FIFO buffer.
In case of reception FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG is
not written to 1 and the data enabled by writing 1 can be cleared. In case of OUT FIFO, the data of
which reception has not been completed can be cleared.
Both sides of the dual-configuration FIFO buffers (EP1 or EP3) can be cleared.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission and reception.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
7, 6
5
4
3 to 1 ⎯
0
Bit
7
6
5
4
Bit Name
⎯
EP3 DE
EP2 DE
EP0iDE
Bit Name
⎯
EP3 CLR
EP1 CLR
EP2 CLR
Initial Value R/W
⎯
⎯
⎯
⎯
Initial Value R/W Description
All 0
0
0
All 0
0
W
W
W
W
R
R
R
R
R
Description
Reserved
The write value should always be 0.
EP3 Clear
EP1 Clear
EP2 Clear
Reserved
These bits are always read as 0.
EP3 Data Enable
EP2 Data Enable
Reserved
These bits are already read as 0.
EP0i data enable
Section 25 USB Function Controller (USBF)
Page 825 of 1414