HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1189

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is
5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the
33.3.3
1. If the L bus is specified as a break condition for data access break, condition comparison is
2. The relationship between the data access cycle address and the comparison condition for each
Table 33.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Access Size
Longword
Word
Byte
ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle.
instruction fetch cycles on the I bus. For details, see No.5 in section 33.3.1, Flow of the User
Break Operation.
performed for the virtual addresses (and data) accessed by the executed instructions, and a
break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition
comparison is performed for the physical addresses (and data) of the data access cycles that are
issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see No.5 in section 33.3.1,
Flow of the User Break Operation.
operand size is listed in table 33.3.
This means that when address H'00001003 is set in the break address register (BARA or
BARB), for example, the bus cycle in which the break condition is satisfied is as follows
(where other conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
Break on Data Access Cycle
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0
Section 33 User Break Controller (UBC)
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