HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 153

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Table 3.4 shows the addresses to be specified in the repeat start register (RS) and repeat end
register (RE).
Table 3.4
Note: The terms used above in table 3.2, are defined as follows.
(2)
To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS
and LDRS instructions and then the number of repetitions must be specified by the SERTC
instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC
instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions.
Table 3.5
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
RS
RE
Instruction
LDRS @(disp,PC)
LDRE @(disp,PC)
SETRC #imm
SETRC Rm
Repeat Control Instructions and Repeat Control Macros
1
RptStart0 + 8
RptStart0 + 4
RptStart: Address of the repeat start instruction
RptStart0: Address of the instruction one instruction prior to the repeat start instruction
RptEnd3: Address of the instruction three instructions prior to the repeat end instruction
RS and RE Setting Rule
Repeat Control Instructions
Calculates (disp x 2 + PC) and stores the result to the
RS register
Calculates (disp x 2 + PC) and stores the result to the
RE register
the SR register and sets the information related to the
number of repetitions to the RF[1:0] bits of the SR.
RC[11:0] can be specified as 0 to 255.
bits of the SR register and sets the information related
to the number of repetitions to the RF[1:0] bits of the
SR.
RC[11:0] can be specified as 0 to 4095.
Operation
Sets 8-bit immediate data imm to the RC[11:0] bits of
Sets the[11:0] bits of the Rm register to the RC[11:0]
2
RptStart0 + 6
RptStart0 + 4
Number of Instructions in Repeat Loop
3
RptStart0 + 4
RptStart0 + 4
Section 3 DSP Operating Unit
≥4
RptStart
RptEnd3 + 4
Number of
Execution States
1
1
1
1
Page 93 of 1414