HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 199

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
(2)
Figure 3.18 shows the logical shift operation flow.
As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand
and the destination operand. The lower word and guard-bit parts are ignored for the source
operand and those of the destination operand are automatically cleared as in the ALU logical
operations. The shift amount is specified by the source 2 operand as an integer data. The source 2
operand can be specified by either the register or immediate operand. The available shift range is
from –16 to +16. Here, a negative value means the right shift, and a positive value means the left
shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown
if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the
source 1 operand must be the same register as the destination’s. These operations are executed in
the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which
memory access is performed.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
39
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.
Shift out
Logical Shift
Cleared to 0
Shift amount data
32 31
(source 2)
39
Left shift
16 15
32 31
Figure 3.18 Logical Shift Operation Flow
0
> = 0
+16 to -16
22 21 16
5
Imm2
0
Sy
< 0
0
15
39
Updated
0
0
32 31
DSR
Shift out
Ignored
Right shift
Section 3 DSP Operating Unit
16 15
GT
Z
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N
V DC
0