HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 108

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.3.4
The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
(1)
The status register (SR) indicates the system status as shown below. The SR register can be
accessed only in privileged mode.
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Bit
31
30
29
Status Register (SR)
Control Registers
Bit Name
⎯
MD
RB
Initial
Value
0
1
1
R/W
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling
state.
Register Bank
The general registers R0 to R7 are banked registers.
0: In this case, R0_BANK0 to R7_BANK0 and R8 to
1: In this case, R0_BANK1 to R7_BANK1 and R8 to
The RB bit is set to 1 in reset or exception handling
state.
R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the
LDC or STR instruction.
R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the
LDC or STR instruction.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010