HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 275

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I
bus. According to the CPU operating mode, access from the CPU is as follows:
(1)
The X/Y memory can be accessed by the DSP directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
(2)
The X/Y memory can be accessed by the DSP directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
6.2.3
The X/Y memory is always accessed by bus master modules such as the DMAC and USB host via
the I bus, which is a physical address bus. Addresses in which the upper three bits are 0 in
addresses shown in table 6.1 must be used.
6.3
6.3.1
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower
X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
6.3.2
The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I
bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of
conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software
measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory
by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be
prevented.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Privileged DSP mode (SR. MD = 1 and SR.DSP = 1)
User DSP mode (SR.MD = 0 and SR.DSP = 1)
Access from Bus Master Module
Usage Notes
Page Conflict
Bus Conflict
Section 6 X/Y Memory
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