HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 157

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(c)
• Repeat control instructions
• Load instructions for SR, RS, and RE registers
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
(d)
Execution of a repeat detection instruction must be completed without any branch so that the CPU
can recognize the repeat loop. Therefore, when the execution branches to an instruction following
the repeat detection instruction, the control will not be passed to a repeat start instruction after
executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this
case, the RC[11:0] bits of the SR register will not be changed.
• If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
• If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 7, Exception Handling.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
detection instruction must be specified as a branch destination.
instruction must be placed before a repeat detection instruction.
Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
instructions)
Branching to an instruction following the repeat detection instruction and restriction
on an exception acceptance
instructions, and the external loop by other instructions such as DT or BF/S.
Section 3 DSP Operating Unit
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