HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 24

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.9
Section 26 LCD Controller (LCDC) .................................................................863
26.1
26.2
26.3
26.4
Page xxiv of lx
Usage Notes ...................................................................................................................... 859
25.9.1
25.9.2
25.9.3
25.9.4
25.9.5
25.9.6
25.9.7
Features............................................................................................................................. 863
Input/Output Pins.............................................................................................................. 865
Register Configuration...................................................................................................... 866
26.3.1
26.3.2
26.3.3
26.3.4
26.3.5
26.3.6
26.3.7
26.3.8
26.3.9
26.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................. 880
26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ..................................... 881
26.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ......................... 882
26.3.13 LCDC Vertical Total Line Number Register (LDVTLNR).............................. 883
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ......................................... 884
26.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ... 885
26.3.16 LCDC Interrupt Control Register (LDINTR) ................................................... 886
26.3.17 LCDC Power Management Mode Register (LDPMMR) ................................. 889
26.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) ............................ 891
26.3.19 LCDC Control Register (LDCNTR)................................................................. 892
26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)........................ 893
26.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ......... 895
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ...................... 896
Operation .......................................................................................................................... 897
26.4.1
26.4.2
26.4.3
Setup Data Reception........................................................................................ 859
FIFO Clear ........................................................................................................ 859
Overreading/Overwriting of Data Register ....................................................... 859
Assigning EP0 Interrupt Sources ...................................................................... 860
FIFO Clear when DMA Transfer is Set ............................................................ 860
Note on Using TR Interrupt .............................................................................. 860
Note on Clock Frequency ................................................................................. 861
LCDC Input Clock Register (LDICKR) ........................................................... 867
LCDC Module Type Register (LDMTR) ......................................................... 868
LCDC Data Format Register (LDDFR)............................................................ 871
LCDC Scan Mode Register (LDSMR) ............................................................. 873
LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ....... 875
LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ....... 876
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ....... 877
LCDC Palette Control Register (LDPALCR)................................................... 878
Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ................................... 879
LCD Module Sizes which can be Displayed in this LCDC .............................. 897
Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (SDRAM) .................................................................. 898
Color Palette Specification ............................................................................... 905
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010