HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 37

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Figure 10.20 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Section 11 Clock Pulse Generator (CPG)
Figure 11.1
Figure 11.2
Figure 11.3
Section 12 Watchdog Timer (WDT)
Figure 12.1
Figure 12.2
Section 13 Power-Down Modes
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10 Hardware Standby Mode Timing (CA is pulled low in normal operation)........... 499
Figure 13.11 Hardware Standby Mode Timing
Figure 13.12 Timing When Power of Pins other than V
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
STATUS Output when Sleep Mode is Canceled by an Interrupt.......................... 496
STATUS Output When Sleep Mode is Canceled by a Power-on Reset ............... 497
STATUS Output When Sleep Mode is Canceled by a Manual Reset................... 497
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time)........................................ 450
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally) .................................................. 450
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time)........................................ 451
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally) .................................................. 452
Block Diagram of CPG......................................................................................... 456
Points for Attention when Using Crystal Resonator ............................................. 469
Points for Attention when Using PLL Oscillator Circuit...................................... 470
Block Diagram of WDT........................................................................................ 472
Writing to WTCNT and WTCSR ......................................................................... 476
Canceling Standby Mode with STBY Bit in STBCR ........................................... 492
STATUS Output at Power-on Reset ..................................................................... 494
STATUS Output at Manual Reset ........................................................................ 494
STATUS Output when Software Standby Mode is Canceled by an Interrupt ...... 495
STATUS Output When Software Standby Mode is Canceled
by a Power-on Reset ............................................................................................. 495
STATUS Output When Software Standby Mode is Canceled
by a Manual Reset................................................................................................. 496
(CA is pulled low while WDT operates after the standby mode is canceled)....... 500
CC
_RTC and V
CC
Q_RTC is Off............ 500
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